This invention relates to a TFT (thin film transistor) matrix device and a method for fabricating the same, especially to a TFT-LCD (TFT matrix liquid crystal display) device and a method for fabricating the same.
TFT-LCDs have characteristics of thinness and lightness, low power consumption, etc. and are expected to have in future a large market as a display device which will take place of CRTs. It is an important subject to develop fabrication technique for realizing high achievement and low prices of TFT-LCDs.
The conventional inverse staggered TFT matrix devices will be explained with reference to FIGS. 17, 18A, 18B, 18C, and 18D.
FIG. 17 is a plan view of a TFT matrix device. FIGS. 18A, 18B, 18C, and 18D are respectively a sectional view of a drain terminal unit along the line A--A' in FIG. 17, a sectional view of a TFT unit along the line B--B' therein, a sectional view of a picture element unit and a storage capacitance unit along the line C--C' therein, and a sectional view of a gate terminal unit along the line D--D' therein.
In the TFT unit of the TFT matrix device, a gate electrode 52a of a metal layer of, e.g., Al (aluminum) or Cr (chrome) or others is formed on a transparent insulating substrate 50. An a-Si (amorphous-silicon) active layer 56a is formed on the gate electrode 52a through a gate insulating film 54a. On the a-Si active layer 56a is formed a channel protecting film 58a, and a source electrode 62a and a drain electrode 62b which connect the a-Si active layer 56a respectively through an n.sup.+ -type a-Si contact layers 60a, 60b. The thus-fabricated TFT is covered by a passivation film 70.
In the picture element unit, a picture element electrode 68a of a transparent conducting film of, e.g., ITO (indium tin oxide) connected to the source electrode 62a is formed and is exposed at a window 72a formed in the passivation film 70.
In the storage capacitance unit, Cs (storage capacitance) electrode 52b of a metal layer of the same material as the gate electrode 52a is formed on the transparent insulating substrate 50. On the Cs electrode 52b is formed a dielectric film 54b of an insulating film 54 which is common with the gate insulating film 54a. The picture element electrode 68a which functions as the counter electrode is formed on the dielectric film 54b. The storage capacitance unit is formed of the Cs electrode 52b and the picture element electrode 68a as the counter electrode which hold the dielectric film 54b therebetween.
In the drain terminal unit, a drain terminal lower electrode 64 is formed of an n.sup.+ -type a-Si layer 60 and a metal layer 62 respectively common with the n.sup.+ -type a-Si contact layer 60b and the drain electrode 62b. A drain terminal upper electrode 68b of the same transparent conducting film as the picture element electrode 68a is formed on the drain terminal lower electrode 64. The drain terminal upper electrode 68b covers the drain terminal lower electrode 64 for preventing the oxidation of the metal film 62 of Al, Cr, or others on the surface of the drain terminal lower electrode 64.
Thus, the drain terminal unit comprises the drain terminal lower electrode 64 connected to the drain electrode 62b through a drain bus line 74, and the drain terminal upper electrode 68b formed on the drain terminal lower electrode 64 and the passivation film 70, and the drain terminal upper electrode 68b is exposed at a window 72b formed in the passivation film 70.
In the gate terminal unit, a gate terminal lower electrode 52d is formed of a metal layer common with the gate electrode 52a and a gate bus line 52c. A gate terminal upper electrode 68c of the same transparent conducting film as the picture element electrode 68a is formed on the gate terminal lower electrode 52d through a contact hole 66 formed in an insulating film 54 common with a gate insulating film 54a formed on the gate terminal lower electrode 52d. The gate terminal upper electrode 68c covers the gate terminal lower electrode 52d for preventing the oxidation of the gate terminal lower electrode 52d of the metal layer of Al, Cr or others.
Thus, the gate terminal unit comprises the gate terminal lower electrode 52d connected to the gate electrode 52a through the gate bus line 52c, and the gate terminal upper electrode 68a formed on the gate terminal lower electrode 52d and the insulating film 54. The gate terminal upper electrode 68c is exposed at a window 72 opened in the passivation film 70.
Next, the method for fabricating the TFT matrix device of FIGS. 17, 18A, 18B, 18C, and 18D will be explained with reference to FIGS. 19A to 28D which are sectional views of the TFT matrix device in its fabrication steps. FIGS. 19A, 20A, . . . , 28A represent the drain terminal unit, FIGS. 19B, 20B, . . . , 28B represent the TFT unit, FIGS. 19C, 20C, . . . , 28C represent the picture element unit and the storage capacitance unit, and FIGS. 19D, 20D, . . . , 28D represent the gate terminal unit respectively along the line A--A' section, the B--B' section, C--C' section and the D--D' section in FIG. 17.
The metal film of, e.g., Al, Cr or others is formed on the transparent insulating substrate 50 and then is provided with a required pattern to form the gate electrode 52a, the Cs electrode 52b, the gate bus line 52c connected to the gate electrode 52a, and the gate terminal lower electrode 52d connected to the gate bus line 52c (FIGS. 19A to 19D).
Then, the insulating film 54 is formed on the entire surface. The insulating film 54 on the gate electrode 52a and the insulating film 54 on the Cs electrode 52b are here especially called a gate insulating film 54a and a dielectric film 54b respectively. Subsequently, a non-doped i-type a-Si film 56 and the protecting film 58 are formed on the insulating film 54 in the stated order (FIGS. 20A to 20D).
Then, the protecting film 58 except a part on the TFT channel unit is etched off. That is, the part of the protecting film 58 only above the gate electrode 52a of the TFT unit is left to form the channel protecting film 58a (FIGS. 21A to 21D).
Then, after the n.sup.+ -type a-Si layer 60 is formed, the metal film 62 of, e.g., Al, Cr or others is formed (FIGS. 22A to 22D).
Then, the metal film 62, the n.sup.+ -type a-Si layer 60, the i-type a-Si layer 56 are selectively etched to form the a-Si active layer 56a of the i-type a-Si layer 56 on the gate insulating film 54a of the TFT unit, and to form the source electrode 62a and the drain electrode 62b of the metal layer 62 connected to the a-Si active layer 56a through the n.sup.+ -type a-Si layers 60a, 60b of the n.sup.+ -type a-Si layer 60 on both sides of the channel protecting film 58a. Thus, the TFT is completed.
At the same time, in the drain terminal unit, the drain terminal lower electrode 64 of the n.sup.+ -type a-Si layer 60 and the metal layer 62 connected to the drain electrode 62b through the drain bus line is formed (FIGS. 23A to 23D).
Then, a resist is applied, and a resist pattern with an opening on the gate terminal lower electrode 52d is formed by lithography. With the resist pattern as a mask, the insulating film 54 is etched to open a contact hole 66 (FIGS. 24A to 24D).
Then, the transparent conducting film 68 of ITO or others is formed (FIGS. 25A to 25D).
Then, a required patterning is provided on the transparent conducting film 68 to form the picture element electrode 68a connected to the source electrode 62, and at the same time the drain terminal upper electrode 68b connected to the drain terminal lower electrode 64 is formed, and the gate terminal upper electrode 68c connected to the gate terminal lower electrode 52d through the contact hole 66 is formed. At this time the picture electrode 68a connected to the source electrode 62a covers the dielectric film 54b on the Cs electrode 52b.
Thus, the storage capacitance unit comprising the Cs electrode 52b, the picture element electrode 68a functioning as the counter electrode to the Cs electrode 52b, and the dielectric film 54b held between these electrodes is completed (FIGS. 26A to 26D).
Then, the passivation film 70 is formed on the entire surface to cover the completed TFT (FIGS. 27A to 27D).
Then, a resist is applied, and then a resist pattern having openings on the picture electrode 68a, the drain terminal upper electrode 68b, and the gate terminal upper electrode 68c is formed by photolithography. With the resist pattern as a mask, the passivation film 70 is etched to open the windows 72a, 72b, 72c to expose the picture element electrode 68a, the drain terminal upper electrode 68b and the gate terminal upper electrode 68c.
Thus, the picture element unit comprising the picture element electrode 68a connected to the source electrode 62a of the TFT, the drain terminal unit comprising the drain terminal upper electrode 68b and the drain terminal lower electrode 64 connected to the drain electrode 62b of the TFT through the drain bus line, and the gate terminal unit comprising the gate terminal upper electrode 68c and the gate terminal lower electrode 52d connected to the gate electrode 52d of the TFT through the gate bus line 52c, are respectively completed (FIGS. 28A to 28D).
In the method for fabricating the above-described conventional TFT matrix device, for forming the gate terminal unit, the gate terminal lower electrode 52d is formed on the transparent insulating substrate 50 (FIGS. 19A to 19D), the insulating film 54 is formed on the gate terminal lower electrode 52d (FIGS. 20A to 20D), the insulating film 54 is etched to open the contact hole 66 (FIGS. 24A to 24D), the gate terminal upper electrode 68c connected to the terminal lower electrode 52d through the contact hole 66 is formed (FIGS. 26A to 26D), the passivation film 70 is formed on the gate terminal upper electrode 68c (FIGS. 27A to 27D), the passivation film 70 is etched to open the opening 72c to expose the upper surface of the gate terminal upper electrode 68c (FIGS. 27A to 27D).
That is, two steps of opening windows: as shown in FIGS. 24A to 24D, selectively etching the insulating film 54 on the gate terminal lower electrode 52d to open the contact hole 66, and as shown in FIGS. 28A to 28D selectively etching the passivation film 70 on the gate terminal upper electrode 68c to open the window 72c, whereby the gate terminal is finally exposed, are necessary.
Each of the two window opening steps includes the lithography step for forming a resist pattern, the etching step, and the resist removing step. It is preferable to realize inexpensive TFT-LCDs that a number of window opening steps is decreased as much as possible to simplify the fabrication process.
In the selectively etching step, as shown in FIGS. 23A to 23D, the metal film 62, the n.sup.+ -type a-Si layer 60, the i-type a-Si active layer 56a are selectively etched to form the a-Si active layer 56a on the gate insulating film 54a of the TFT unit, and to form the source electrode 62a and the drain electrode 62b connected to the a-Si active layer 56a respectively through the n.sup.+ -type a-Si contact layers 60a, 60b, the dielectric film 54b on the Cs electrode 52b is exposed directly to an etchant, and a thickness of the dielectric film 54b changes, and accordingly a storage capacitance changes adversely.
At this time, pin holes or others in a part of the dielectric film 54b cause a risk that etchant may intrude into the pin holes or others, with a result that defective insulation takes place in the dielectric film 54b, causing current leakage and short circuits between the Cs electrode 52b and the picture element electrode 68a as its counter electrode which result in defective displays.